S29NS-P Datasheet, PDF (74/86 Pages) SPANSION – MirrorBit Flash Family

Data Sheet (Advance Information)
Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings
CE#
CLK
AVD#
Amax–
VA
VA
A16
OE#
A/DQ15–
A/DQ0
VA
t_IACC
Status Data
VA
t_IACC
Status Data
RDY
Notes
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle
bits stop toggling.
3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle
before data.
WE#
Figure 10.18 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
DQ6
Erase
Complete
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 10.19 Latency with Boundary Crossing
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
Address _7C
7D
7E
7F
7F
80
81
82
83
(hex)
CLK
AVD# (stays high)
RDY
(Note 1)
RDY
(Note 2)
Data
D124
t_RACC
t_RACC
latency
t_RACC
latency
t_RACC
D125 D126 D127 Invalid D128
OE#,
CE#
(stays low)
Notes
1. RDY active with data (CR0.8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (CR0.8 = 1 in the Configuration Register).
3. Figure shows the device not crossing a bank in the process of performing an erase or program.
D129 D130
74
S29NS-P MirrorBit^TM Flash Family
S29NS-P_00_A1 February 20, 2007