S29GL-N_07 Datasheet, PDF (73/79 Pages) SPANSION – 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology

Data Sheet
16. Erase And Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
S29GL032N
S29GL064N
Total Write Buffer Program Time (Notes 3, 5)
Total Accelerated Effective Write Buffer Program Time (Notes 4, 5)
Chip Program Time
S29GL032N
S29GL064N
Typ (Note 1)
0.5
32
64
240
200
31.5
63
Max
(Note 2)
3.5
64
128
Unit
Comments
Excludes 00h
programming prior
sec
to erasure
(Note 6)
µs
Excludes system
level overhead
sec
(Note 7)
Notes
1. Typical program and erase times assume the following conditions: 25°C, V_CC = 3.0V, 10,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C; Worst case V_CC, 100,000 cycles.
3. Programming time (typ) is 15 μs (per word), 7.5 μs (per byte).
4. Accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).
5. Write buffer Programming time is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.1 on page 51 and Table 10.3
on page 53 for further information on command definitions.
Table 16.1 TSOP Pin and BGA Package Capacitance
Parameter Symbol
C_IN
Parameter Description
Input Capacitance
C_OUT
Output Capacitance
C_IN2
Control Pin Capacitance
C_IN3
#RESET, #WP/ACC Pin Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions T_A = 25°C, f = 1.0 MHz.
Test Setup
V_IN = 0
TSOP
BGA
V_OUT = 0
TSOP
BGA
V_IN = 0
TSOP
BGA
V_IN = 0
TSOP
BGA
Typ
6
TBD
6
TBD
6
TBD
27
TBD
Max
Unit
10
pF
TBD
pF
12
pF
TBD
pF
10
pF
TBD
pF
30
pF
TBD
pF
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit^® Flash Family
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