S6E2HE Datasheet, PDF (71/163 Pages) SPANSION – fpu built-in

S6E2HE Series
12.2 Recommended Operating Conditions
Parameter
Symbol Conditions
Value
Min
Max
Power supply voltage
VCC
-
2.7*4
5.5
Power supply voltage (VBAT)
VBAT
-
2.7
5.5
Analog power supply voltage
AVCC
-
2.7
5.5
Analog reference voltage
AVRH
-
*3
AVCC
Smoothing capacitor
CS
-
1
10
Operating
Junction temperature
TJ
-
- 40
+ 125
temperature Ambient temperature
TA
-
- 40
*2
*1: See "●C pin" in "Handling Devices" for the connection of the smoothing capacitor.
Unit
Remarks
V
V
V AVCC=VCC
V
μF for built-in regulator *1
°C
°C
*2: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed
the junction temperature (TJ).
The calculation formula of the ambient temperature (TA) is shown below.
TA (Max) = TJ (Max) - Pd(Max) × θja
Pd:
Power dissipation (W)
θja:
Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL:
IOH:
VOL:
VOH:
L level output current
H level output current
L level output voltage
H level output voltage
*3:The minimum value of Analog reference voltage depends on the value of compare clock cycle
(Tcck). See 12.5 12-bit A/D Converter for the details.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR
is possible to operate only.
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Package
Printed Circuit Board
Thermal Resistance
θja (°C/W)
Maximum Permissible Power
(mW)
TA=+85°C
TA=+105°C
LQH080
Single-layered both sides
82
488
244
(0.5-mm pitch)
4 layers
56
714
357
LQI100
Single-layered both sides
59
678
339
(0.5-mm pitch)
4 layers
39
1026
513
LQM120
Single-layered both sides
71
563
282
(0.5-mm pitch)
4 layers
50
800
400
FDI121
Single-layered both sides
63
635
317
(0.5-mm pitch)
4 layers
37
1081
540
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
Document Number: 001-98942 Rev.*A
Page 71 of 163