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S6E2HE Datasheet, PDF (1/163 Pages) SPANSION – fpu built-in | |||
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S6E2HE Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2HE Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. These
series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
Features
32-bit ARM Cortex-M4F Core
ï®Processor version: r0p1
ï®Up to 160 MHz Frequency Operation
ï®FPU built-in
ï®Support DSP instruction
ï®Memory Protection Unit (MPU): improves the reliability of an
embedded system
ï®Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
ï®24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
ï®Flash memory
These series are based on two independent on-chip Flash
memories.
ï¯ MainFlash memory
⢠Up to 512 Kbytes
⢠Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
⢠The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
⢠Security function for code protection
ï¯ WorkFlash memory
⢠32 Kbytes
⢠Read cycle:
⢠6 wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
⢠4 wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
⢠2 wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
⢠0 wait-cycle: the operation frequency up to 40 MHz
⢠Security function is shared with code protection
ï® SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
ï¯ SRAM0: Up to 32 Kbytes
ï¯ SRAM1: Up to 16 Kbytes
ï¯ SRAM2: Up to 16 Kbytes
External Bus Interface
ï®Supports SRAM, NOR, NAND Flash and SDRAM device
ï®Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
ï®8-/16-bit Data width
ï®Up to 25-bit Address bit
ï®Supports Address/Data multiplex
ï®Supports external RDY function
ï®Supports scramble function
⢠Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
⢠Possible to set two kinds of the scramble key
⢠Note: It is necessary to prepare the dedicated software
library to use the scramble function.
Multi-function Serial Interface (Max 8 channels)
ï®64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
ï®Operation mode is selectable from the followings for each
channel.
ï¯ UART
ï¯ CSIO
ï¯ LIN
ï¯ I2C
ï® UART
ï¯ Full-duplex double buffer
ï¯ Selection with or without parity supported
ï¯ Built-in dedicated baud rate generator
ï¯ External clock available as a serial clock
ï¯ Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
Cypress Semiconductor Corporation
Document Number: 001-98942 Rev.*A
⢠198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised October 8, 2015
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