S29WS-J Datasheet, PDF (66/97 Pages) SPANSION – 128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

Data Sheet
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to Table 19, “DQ6 and DQ2 Indications,” on
page 66 to compare outputs for DQ2 and DQ6.
See the following for additional information: Figure 8, “Toggle Bit Algorithm,” on page 65, See
DQ6: Toggle Bit I on page 64, Figure 30, “Toggle Bit Timings (During Embedded Algorithm),” on
page 87, and Table 19, “DQ6 and DQ2 Indications,” on page 66.
If device is
programming,
actively erasing,
erase suspended,
programming in
erase suspend
Table 19. DQ6 and DQ2 Indications
and the system reads
at any address,
then DQ6
toggles,
and DQ2
does not toggle.
at an address within a sector
selected for erasure,
toggles,
also toggles.
at an address within sectors not
selected for erasure,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
does not toggle,
toggles.
at an address within sectors not
selected for erasure,
returns array data,
returns array data. The system can read
from any sector not selected for erasure.
at any address,
toggles,
is not applicable.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8, “Toggle Bit Algorithm,” on page 65 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value
of the toggle bit after the first read. After the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (Figure 8, “Toggle Bit
Algorithm,” on page 65).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was
not successfully completed.
66
S29WS128J/064J
S29WS-J_00_A6 May 11, 2006