S71AL016D Datasheet, PDF (64/76 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Preliminary
Timing Diagrams
Address
t_RC
t_AA
t_OH
Data Out
Previous Data Valid
Data Valid
Figure 2. Timing of Read Cycle (CE# = OE# = V_IL, WE# = CE2= V_IH)
Address
CE1#
CE2
OE#
LB#, UB#
Data Out
t_RC
t_AA
t_HZ
t_CO
t_LZ
t_OE
t_OHZ
t_OLZ
t_LB, t_UB
t_LBLZ, t_UBLZ
High-Z
t_LBHZ, t_UBHZ
Data Valid
Figure 3. Timing Waveform of Read Cycle (WE# = V_IH)
64
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004