S25FL256SAGMFI000 Datasheet, PDF (62/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O

Data Sheet
8.5.3
8.5.4
Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit -
Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not
monitored for their normal functions and are internally set to high (inactive). The commands for Serial, Dual
Output, and Dual I/O Read still function normally but, there is no need to drive WP# and Hold# inputs for
those commands when switching between commands using different data path widths. The QUAD bit must
be set to one when using Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program
commands. The QUAD bit is non-volatile.
Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits
in Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address
space. This prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains
cleared to logic 0 the other bits of the Configuration Register, including FREEZE, are writable, and the OTP
address space is programmable. Once the FREEZE bit has been written to a logic 1 it can only be cleared to
a logic 0 by a power-off to power-on cycle or a hardware reset. Software reset will not affect the state of the
FREEZE bit. The FREEZE bit is volatile and the default state of FREEZE after power-on is 0. The FREEZE bit
can be set in parallel with updating other values in CR1 by a single WRR command.
Status Register 2 (SR2)
Related Commands: Read Status Register 2 (RDSR2 07h).
Table 8.14 Status Register-2 (SR2)
Bits
Field Name
Function
Type
Default State
Description
7
RFU
Reserved
0
Reserved for Future Use
6
RFU
Reserved
0
Reserved for Future Use
5
RFU
Reserved
0
Reserved for Future Use
4
RFU
Reserved
0
Reserved for Future Use
3
RFU
Reserved
0
Reserved for Future Use
2
RFU
Reserved
0
Reserved for Future Use
1 = In erase suspend mode
1
ES
Erase Suspend Volatile, Read only
0
0 = Not in erase suspend mode
0
PS
Program
Suspend
Volatile, Read only
1 = In program suspend mode
0
0 = Not in program suspend mode
Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase
Suspend mode. This is a status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in
erase suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase suspend mode.
Refer to Erase Suspend and Resume Commands (75h) (7Ah) for details about the Erase Suspend/Resume
commands.
Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in
Program Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to 1, the
device is in program suspend mode. When the Program Suspend bit is cleared to 0, the device is not in
program suspend mode. Refer to Program Suspend (PGSP 85h) and Resume (PGRS 8Ah) on page 114 for
details.
AutoBoot Register
Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).
The AutoBoot Register provides a means to automatically read boot code as part of the power on reset,
hardware reset, or software reset process.
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S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012