S25FL256SAGMFI000 Datasheet, PDF (44/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O

Data Sheet
6.5
DDR AC Characteristics
Table 6.6 AC Characteristics 66 MHz Operation
Symbol
Parameter
Min
Typ
Max
Unit
F_{SCK, R} SCK Clock Frequency for DDR READ instruction
DC
P_{SCK, R} SCK Clock Period for DDR READ instruction
15
66 (3)

MHz
ns
t_crt
t_cft
t_WH, t_CH
t_WL, t_CL
t_CS
t_CSS
t_CSH
t_SU
t_HD
t_V
t_HO
t_DIS
t_LZ
t_IHTU
t_ILTU
t_{IO_skew}
t_IORT
t_IOFT
T_V
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
Clock High Time
Clock Low Time
CS# High Time (Read Instructions)
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
IO in Setup Time
IO in Hold Time
Clock Low to Output Valid
Output Hold Time
Output Disable Time
Clock to Output Low Impedance
Time uncertainty due to variation in V_IH
Time uncertainty due to variation in V_IL
First IO to last IO data valid time
Output rise time given 3V swing and 2.0 V/ns slew
Output fall time given 3V swing and 2.0 V/ns slew
Clock to data valid jitter
1.5
1.5
45% P_SCK
45% P_SCK
10
3
3
2
2
0
0
0
3000 (2)
6.5 (1)
8
8
50
50
600
1.5
1.5
25
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
ps
Note:
1. Regulated V_CC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
3. For Automotive In-Cabin temperature range (-40°C to +105°C), all SCK clock frequencies are 5% slower than the Max values shown.
44
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012