S25FL512SAGMFI010 Datasheet, PDF (57/140 Pages) SPANSION – 512 Mbit (64 Mbyte) MirrorBit® Flash Non-Volatile Memory

Data Sheet
8.6
Registers
Registers are small groups of memory cells used to configure how the S25FL512-S memory device operates
or to report the status of device operations. The registers are accessed by specific commands. The
commands (and hexadecimal instruction codes) used for each register are noted in each register description.
The individual register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for
each bit is noted in each register description. The default state shown for each bit refers to the state after
power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the
default state is the value of the bit when the device is shipped from Spansion. Non-volatile bits have the same
cycling (erase and program) endurance as the main flash array.
8.6.1
Status Register 1 (SR1)
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN
06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).
Table 8.3 Status Register-1 (SR1)
Bits
Field
Name
Function
Type
Default State
Description
7
SRWD
Status Register
Write Disable
Non-Volatile
1 = Locks state of SRWD, BP, and configuration register
0
bits when WP# is low by ignoring WRR command
0 = No protection, even when WP# is low
6
P_ERR
Programming
Error Occurred
Volatile, Read only
0
1 = Error occurred.
0 = No Error
5
E_ERR
Erase Error
Occurred
Volatile, Read only
1 = Error occurred
0
0 = No Error
4
BP2
1 if CR1[3]=1,
3
2
BP1
BP0
Block
Protection
Volatile if CR1[3]=1,
Non-Volatile if
CR1[3]=0
0 when
shipped from
Spansion
Protects selected range of sectors (Block) from Program
or Erase
1
WEL
Write Enable
Latch
Volatile
1 = Device accepts Write Registers (WRR), program or
erase commands
0
0 = Device ignores Write Registers (WRR), program or
erase commands
This bit is not affected by WRR, only WREN and WRDI
commands affect this bit
0
WIP
Write in
Progress
Volatile, Read only
1 = Device Busy, a Write Registers (WRR), program,
0
erase or other operation is in progress
0 = Ready Device is in standby mode and can accept
commands
The Status Register contains both status and control bits:
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when
this bit is set to 1 and the WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the
Status Register become read-only bits and the Write Registers (WRR) command is no longer accepted for
execution. If WP# is high the SRWD bit and BP bits may be changed by the WRR command. If SRWD is 0,
WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The SRWD bit
has the same non-volatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure
indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program
operation. This bit will also be set when the user attempts to program within a protected main memory sector
or locked OTP region. When the Program Error bit is set to a 1 this bit can be reset to 0 with the Clear Status
Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure
indication. When the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation.
This bit will also be set when the user attempts to erase an individual protected main memory sector. The
Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When
the Erase Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register (CLSR) command. This
is a read-only bit and is not affected by the WRR command.
January 8, 2014 S25FL512S_00_07
S25FL512S
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