S25FL512SAGMFI010 Datasheet, PDF (114/140 Pages) SPANSION – 512 Mbit (64 Mbyte) MirrorBit® Flash Non-Volatile Memory

Data Sheet
The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP
command is not executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is
initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PPBP operation, and
is a 0 when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a
0.
Figure 10.66 PPBP (E3h) Command Sequence
CS#
SCK
SI
SO
Phase
7
6
5
4
3
2
1
0
31
Instruction
1
0
Address
10.8.7
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by
the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the
Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of
the entire PPB memory array. Without CS# being driven to the logic high state after the eighth bit of the
instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to
check if the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress
and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.
CS#
SCK
SI
SO
Phase
Figure 10.67 PPB Erase (PPBE E4h) Command Sequence
7
6
5
4
3
2
1
0
Instruction
10.8.8
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is
possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock
Register contents may only be read when the device is in standby state with no other operation in progress. It
is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new
command to the device.
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S25FL512S
S25FL512S_00_07 January 8, 2014