S25FL132K Datasheet, PDF (48/85 Pages) SPANSION – CMOS 3.0-Volt Flash Non-Volatile Memory Serial Peripheral Interface with Multi-I/O Industrial and Automotive Temperature

Data Sheet (Preliminary)
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Bits
Field
Name
Function
7
RFU
Reserved
6
W6
Burst Wrap
5
W5
Length
4
W4
Burst Wrap
Enable
3
2
Latency Variable Read
Control
Latency
1
(LC)
Control
0
Table 7.7 Status Register-3 (SR3)
Type
Volatile
Default State
Description
0
Reserved for Future Use
1
00 = 8-byte wrap. Data read starts at the initial address
and wraps within an aligned 8-byte boundary
01 = 16-byte wrap. Data read starts at the initial address
and wraps within an aligned 16-byte boundary.
1
10 = 32-byte wrap. Data read starts at the initial address
and wraps within an aligned 32-byte boundary.
11 = 64-byte wrap. Data read starts at the initial address
and wraps within an aligned 64-byte boundary.
0 = Wrap Enabled
1
1 = Wrap Disabled
0
Defines the number of read latency cycles in Fast Read,
0
Dual Out, Quad Out, Dual IO, and Quad IO commands.
0
Binary values for 1 to 15 latency cycles. A value of zero
disables the variable latency mode.
0
BUSY
BUSY is a read only bit in the Status Register (SR1[0]) that is set to a 1 state when the device is executing a
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Registers or Erase / Program Security
Register command. During this time the device will ignore further commands except for the Read Status
Register and Erase / Program Suspend command (see t_W, t_PP, t_SE, t_BE, and t_CE in Section 5.7, AC Electrical
Characteristics on page 31). When the program, erase or write status / security register command has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further commands.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the Status Register (SR1[1]) that is set to 1 after executing a
Write Enable Command. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following commands: Write Disable, Page Program, Sector
Erase, Block Erase, Chip Erase, Write Status Registers, Erase Security Register and Program Security
Register. The WEL status bit is cleared to 0 even when a program or erase operation is prevented by the
block protection bits. The WEL status bit is also cleared to 0 when a program or erase operation is
suspended. The WEL status bit is set to 1 when a program or erase operation is resumed.
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers
Command (see t_W in Section 5.7, AC Electrical Characteristics on page 31). All, none or a portion of the
memory array can be protected from Program and Erase commands (see Section 7.4.7, Block Protection
Maps on page 49). The factory default setting for the Block Protection Bits is 0 (none of the array is
protected.)
Top / Bottom Block Protect (TB)
The non-volatile Top / Bottom bit (TB SR1[5]) controls if the Block Protect Bits (BP2, BP1, BP0) protect from
the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 7.4.7, Block Protection Maps
on page 49. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers
Command depending on the state of the SRP0, SRP1 and WEL bits.
Sector / Block Protect (SEC)
The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the
array as shown in Section 7.4.7, Block Protection Maps on page 49. The default setting is SEC=0.
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S25FL132K and S25FL164K
S25FL132K_164K_00_03 October 16, 2013