MBM29BS12DH15 Datasheet, PDF (48/84 Pages) SPANSION – BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT

MBM29BS/FS12DH15
s AC CHARACTERISTICS
• Synchronous/Burst Read
Parameter
Latency (Even Address in Handshake Mode)
Latency—(Non-Handshake or Odd
Address in Handshake mode)
Burst Access Time Valid Clock to Output Delay
Address Setup Time to CLK*
Address Hold Time from CLK*
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High-Z
Output Enable to High-Z
CE Setup Time to CLK
Ready Access Time from CLK
CE Setup Time to AVD
AVD Set Up Time to CLK
AVD Hold Time to CLK
Access Time
CLK to access resume
CLK to High-Z
Output Enable Setup Time
Read Cycle for Continuous suspend
Read Cycle Time
*: Addresses are latched on the active edge of CLK.
Note : Test Conditions:
Output Load: VCCQ = 1.65 V to 1.95 V : 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCQ
Timing measurement reference level
Input: 0.5 × VCCQ
Output: 0.5 × VCCQ
Symbols
Standard
tIACC
tIACC
tBACC
tACS
tACH
tBDH
tCR
tOE
tCEZ
tOEZ
tCES
tRACC
tCAS
tAVSC
tAVHC
tACC
tCKA
tCKZ
tOES
tRCC
tRC
Value
54 MHz
66 MHz Unit
Min Max Min Max
— 69 — 56 ns
— 87.5 — 71 ns
— 13.5 — 11 ns
5
—
4
— ns
7
—
6
— ns
4
—
3
— ns
— 13.5 — 11 ns
— 13.5 — 11 ns
— 10 —
8
ns
— 10 —
8
ns
5
——
4
ns
— 13.5 — 11 ns
0
—
0
— ns
5
—
4
— ns
7
—
6
— ns
— 55 — 50 ns
— 13.5 — 11 ns
— 10 —
8
ns
5
—
4
— ns
—
1
—
1 ms
55 — 50 — ns
48