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| AM50DL128CG Datasheet, PDF (44/63 Pages) SPANSION – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM | |||
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PRELIMINARY
FLASH AC CHARACTERISTICS
Erase and Program Operations
Parameter
JEDEC
Std Description
tAVAV
tAVWL
tWLAX
tWC Write Cycle Time (Note 1)
Min
tAS Address Setup Time
Min
tASO Address Setup Time to OE# low during toggle bit polling
Min
tAH Address Hold Time
Min
tAHT
Address Hold Time From CE#f or OE# high
during toggle bit polling
Min
tDVWH
tDS Data Setup Time
Min
tWHDX
tDH Data Hold Time
Min
tOEPH Output Enable High during toggle bit polling
Min
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
tWLEL
tWS WE# Setup Time (CE#f to WE#)
Min
tELWL
tCS CE#f Setup Time
Min
tEHWH
tWH WE# Hold Time (CE#f to WE#)
Min
tWHEH
tCH CE#f Hold Time
Min
tWLWH
tWP Write Pulse Width
Min
tWHDL
tWPH Write Pulse Width High
Min
tSR/W Latency Between Read and Write Operations
Min
tWHWH1
tWHWH1 Programming Operation (Note 2)
Word
Typ
tWHWH1
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
tVCS VCC Setup Time (Note 1)
Min
tRB Write Recovery Time from RY/BY#
Min
tBUSY Program/Erase Valid to RY/BY# Delay
Max
Notes:
1. Not 100% tested.
2. See the âFlash Erase And Programming Performanceâ section for more information.
3. CE#f refers to chip enable input of active flash (device being addressed).
Speed
70
85
Unit
70
85
ns
0
ns
15
ns
40
45
ns
0
ns
40
45
ns
0
ns
20
ns
0
ns
0
ns
0
ns
0
ns
0
ns
30
35
ns
30
ns
0
ns
7
µs
4
µs
0.4
sec
50
µs
0
ns
90
ns
November 7, 2002
Am50DL128CG
43
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