S29GL512P12TFIV20 Datasheet, PDF (40/81 Pages) SPANSION – 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology

Data Sheet
Table 7.17 Write Operation Status
Status
DQ7
(Note 2)
DQ6
DQ5
DQ2
RY/
(Note 1) DQ3 (Note 2) DQ1 BY#
Standard ^{Embedded Program Algorithm DQ7# Toggle}
0
N/A No toggle 0
0
Mode
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Program-Suspended
Program Program-
Sector
Invalid (not allowed)
1
Suspend Suspend
Mode
Read
Non-Program
Suspended Sector
Data
1
Erase
Suspend
Mode
Erase-
Suspend
Read
Erase-Suspended
Sector
Non-Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
N/A
1
Data
1
Erase-Suspend-Program
(Embedded Program)
DQ7# Toggle
0
N/A
N/A
N/A
0
Write-to-
Buffer
Busy (Note 3)
Abort (Note 4)
DQ7# Toggle
0
N/A
N/A
DQ7# Toggle
0
N/A
N/A
0
0
1
0
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
Refer toDQ5: Exceeded Timing Limits on page 39 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
7.9 Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to V_IL and OE# to V_IH when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device. Table 6.1 – Table 6.4 indicate the address space that each sector occupies. The device
address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits
required to uniquely select a sector. I_CC2 in “DC Characteristics” represents the active current specification for
the write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
7.9.1
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V_CC. This feature allows the host system to detect when data is ready to be read by simply
monitoring the RY/BY# pin, which is a dedicated output.
7.9.2
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t_RP (RESET# Pulse Width), the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading
array data.
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at V_SS, the device draws V_CC reset current (I_CC5). If RESET# is held at V_IL, but not at
V_SS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the
system to read the boot-up firmware from the Flash memory upon a system reset. See Figure 11.7
on page 59 and Figure 11.8 on page 60 for timing diagrams.
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S29GL-P MirrorBit^® Flash Family
S29GL-P_00_A14 October 22, 2012