S30MS-P Datasheet, PDF (31/41 Pages) SPANSION – 1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBit™ Technology

Data Sheet (Preliminary)
register. The Read Status command (70h) may be issued to verify that the cache register is ready by polling
the Cache-Busy status bit (I/O6). Pass/Fail status of the previous page is available upon the return to the
Ready state. When the next set of data is input with the Cache Program command, t_CBSY is affected by the
progress of pending internal programming. The programming of the cache register is initiated only when the
pending program cycle is finished and the data register is available for the transfer of data from the cache
register. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal
programming.
If the system monitors the progress of programming with RY/BY# only, the last page of the target
programming sequence must be programmed with Page Program command (10h). Alternatively, if the last
page to be programmed is accomplished using the Cache Program command (15h), status bit (I/O5) must be
polled to verify that the last program is actually finished before starting other operations.
Following the Cache Program Command (15h), the pass/fail status information is available as follows:
1. I/O1 returns the status of the previous page (when ready or when the I/O6 bit is changing to a 1).
2. I/O0 returns the status of the current page (upon true ready, or when the IO5 bit is changing to a 1).
3. I/O0 and I/O1 may be read together.
Figure 12.5 Cache Program
RY/BY#
tCBSY1
tCBSY2
tCBSY2
tPROG
80h
Address &
15h
80h
Data Input*
Address &
Data Input
15h
80h
Address &
Data Input
15h
80h
Address &
10h
Data Input
70h
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
RY/BY#
tCBSY1
tCBSY2
tCBSY2
I/Ox
80h
Address &
Data Input
15h
70h
Col Add1,2 & Row Add1,2
Data
Status
output
80h
Address &
Data Input
15h
Col Add1,2 & Row Add1,2
Data
tCBSY2
70h
Status
output
80h
Address &
Data Input
15h
Col Add1,2 & Row Add1,2
Data
70h
Status
output
80h
Address &
Data Input
15h
Col Add1,2 & Row Add1,2
Data
70h
Status
output
Status
output
Check I/O1 for pass/fail
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
Note:
Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous
program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous
cycle, which can be expressed as the following formula: t_PROG = Program time of last page + program time of the (last -1) page - (program
command time + data loading time of last page).
12.4
Page Duplicate Program
The Page Duplicate program is configured to quickly and efficiently rewrite data stored in one full page (no
partial page) without utilizing an external memory. Since the time-consuming serial access and re-loading
cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of
a block is updated and the block also needs to be copied to the newly assigned free block. A Page Duplicate
program operation is performed by first initiating a read operation with command 35h and the address of the
source which then duplicates the whole 2112Byte (x8) or 1056Word (x16) data into the internal data buffer.
As soon as the device is ready, the Program Confirm command (10h) is required to actually begin the
programming operation to the address of the destination page. Once the Page Duplicate Program is finished,
any additional partial page programming into the copied pages is prohibited before erasure. The data input
cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 12.6
on page 30. Page data duplicates directly to another Page in a Block.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNAND^TM Flash Family
29