S29AL016M Datasheet, PDF (12/59 Pages) SPANSION – 16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY

The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V_CC ± 0.3 V. (Note that this is a more restricted voltage range than
V_IH.) If CE# and RESET# are held at V_IH, but not within V_CC ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t_CE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I_CC3 and I_CC4 represents the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The
device automatically enables this mode when addresses remain stable for t_ACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output data is latched and always
available to the system. I_CC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V_IL for at least a period of
t_RP, the device immediately terminates any operation in progress, tristates all
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V_SS±0.3 V, the device draws CMOS standby current (I_CC4). If RESET# is held
at V_IL but not within V_SS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t_READY (during Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t_READY (not during Embedded
Algorithms). The system can read data t_RH after the RESET# pin returns to V_IH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14
for the timing diagram.
Output Disable Mode
When the OE# input is at V_IH, output from the device is disabled. The output pins
are placed in the high impedance state.
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S29AL016M
S29AL016M_00A4 April 21, 2004