S71GS256 Datasheet, PDF (104/195 Pages) SPANSION – 128N based MCPs

Advance Information
that part of the DRAM array that contains essential data. Temperature compen-
sated refresh (TCR) adjusts the refresh rate to match the device temperature—
the refresh rate decreases at lower temperatures to minimize current consump-
tion during standby. Deep power-down (DPD) enables the system to halt the
refresh operation altogether when no vital information is stored in the device. The
system-configurable refresh mechanisms are accessed through the RCR.
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Decode
Logic
Refresh Configuration
Register (RCR)
DRAM
MEMORY
ARRAY
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
Control
Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
Figure 21. Functional Block Diagram
104
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004