S25FL512S Datasheet, PDF (103/143 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet (Preliminary)
value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is
enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left
high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
There are different ordering part numbers that select the latency code table used for this command, either the
High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of
dummy cycles is determined by the frequency of SCK (refer to Table 8.6, Latency Codes for DDR High
Performance on page 58). The number of dummy cycles is set by the LC bits in the Configuration Register
(CR1).
Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8
bit instruction after the first command sends a complementary mode bit pattern, as shown in Figure 10.47 and
Figure 10.49. This feature removes the need for the eight bit SDR instruction sequence and dramatically
reduces initial access times (improves XIP performance). The Mode bits control the length of the next Read
DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the upper
nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device
transitions to Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is
raised high and then asserted low) without requiring the EDh or EEh instruction, as shown in Figure 10.48
on page 104 and Figure 10.50 on page 104 thus, eliminating eight cycles from the command sequence. The
following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the
device can accept standard SPI commands:
1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the
next time CS# is raised high and then asserted low the device will be released from Read DDR
Quad I/O mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input
(IO0, IO1, IO2, and IO3) are not set for a valid instruction sequence, then the device will be
released from Read DDR Quad I/O mode.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during Quad I/O DDR commands.
Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a
pattern that is used by the host controller to optimize data capture at higher frequencies. The preamble drives
the IO bus for the four clock cycles immediately before data is output. The host must be sure to stop driving
the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host
controller will skew the data capture point during the preamble period to optimize timing margins and then use
the same skew time to capture the data during the rest of the read operation. The optimized capture point will
be determined during the preamble period of every read operation. This optimization strategy is intended to
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4
device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See SPI DDR Data Learning Registers
on page 63 for more details.
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