XPP-XG-N2-CDFA Datasheet, PDF (4/12 Pages) –

XPP-XG-N2-CDFA
RSSI Trigger Delay
RSSI Sampling Time
Internal I²C Delay
Ttrigger
25
ns
7
T__sampling
TI2C
600
ns
8
500
ms
Notes:
1. Compatible with CML input, AC coupled internally. (See Recommended Interface Circuit)
2. TX Disable (See Pin Function Definitions).
3. CML output, DC coupled internally, guaranteed in the full range of input optical power (-11dBm to
-27.5dBm) (See Recommended Interface Circuit).
4. LOS (See Pin Function Definitions).
5. Amount time is from the reset signal is coming to the bust signal reaches a appropriate value
6. Test at 0101 pattern@2.5Gbps, 20% to 80% full swing
7. Falling edge of reset signal should be after the rising edge of the first preamble bit, test@1010 pattern
8. RSSI Input signal rising edge will trigger RSSI sampling, and falling edge will trigger internal digital
RSSI information written to I2C. It is recommended that host shall not trigger RSSI input again until
RSSI data is valid in I2C from previous RSSI trigger.
ONT #1
Guard Time
Max 16 bytes
Physical Overload (141 bytes)[1]
Preamble Time
121 bytes
Delimiter
4 bytes
ONT #2
Reset
SD
RX Output
TSDD
0-2
bytes
TSDA
10 bytes
Settling Time
43
bytes(max)
Transient
(4 bytes)
Valid Preamble to CDR or CPA
74 bytes
Note:
The bytes means that ONT rate is 2.488Gbps, 1bytes=3.2ns
Figure 1, Timing Parameter Definition in Burst Mode Sequence (Dual ONT Application)
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DS- 6774 Rev 01 2011-10-27