CXD1818R Datasheet, PDF (71/112 Pages) Sony Corporation – CD-ROM Decoder

CXD1818R
1-3-7. 76h
(1) INTEN2 (interrupt enable 2) register (read/write)
INTEN2 (interrupt enable 2) register
Adr.
76h (R/W)
bit7
FUNC
CMPL
0
bit6
CMD
IGNR
0
bit5
SCSI
RST
0
bit4
ATN
COND
0
bit3
SCSI
PERR
0
bit2
SLW
ATN
0
bit1
SLWO
ATN
0
bit0
RSL
FAIL
0
Reg.
INTEN2
Initial value
Setting each bit of this register high enables interrupt requests to the sub CPU from this IC in response to the
corresponding interrupt status. (In other words, if that interrupt status results, the INT pin goes active.) The
value of each bit in this register has no effect on their corresponding interrupt status.
bit 7:
FUNCCMPL (function complete)
bit 6:
CMDIGNR (command ignored)
bit 5:
SCSIRST (SCSI reset)
bit 4:
ATNCOND (ATN condition)
bit 3:
SCSIPERR (SCSI parity error)
bit 2:
SLWATN (selection with ATN)
bit 1:
SLWOATN (selection without ATN)
bit 0:
RSLFAIL (Reselection fail)
1-3-8. 77h
(1) INTEN3 (interrupt enable 3) register (read/write)
INTEN3 (interrupt enable 3) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
77h (R/W)
SCAM SCAM
INIF
SL
INTEN3
0
0
Initial value
Setting each bit of this register high enables interrupt requests to the sub CPU from this IC in response to the
corresponding interrupt status. (In other words, if that interrupt status results, the INT pin goes active.) The
value of each bit in this register has no effect on their corresponding interrupt status.
bit 1:
SCAMINIF (SCAM initiation fail)
bit 0:
SCAMSL (SCAM selection)
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