CXD1818R Datasheet, PDF (40/112 Pages) Sony Corporation – CD-ROM Decoder

CXD1818R
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
RPCORTRG (repeat correction trigger)
If this bit is set high while the decoder is disabled, the CD-ROM sector error correction begins. The
sector that is corrected is specified by the BFARA# register.
BFSTOP (buffering stop)
When this bit is set high, buffering the data from the CD DSP is stopped. This bit is used when the
Short sync occurs during execution of the asynchronous correction command, and the like.
CLDSPCMD (clear DSP data register)
Setting this bit high clears the DSPCMD register.
DSPCMDXF (DSP command transfer)
Setting this bit high starts serial transfer of the contents of the DSPCMD register to the CD DSP.
DSPCMDLT (DSP command latch)
Setting this bit high outputs a pulse from the XLAT pin.
1-1-24. 19h
(1) CPUBRDT (CPU buffer read data) register (read)
CPUBRDT (CPU buffer read data) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
19h (R)
The sub CPU reads the Data In the buffer memory through this register.
Reg.
CPUBRDT
(2) CPUBWDT (CPU buffer write data) register (write)
CPUBWDT (CPU buffer write data) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
19h (W)
b7
b6
b5
b4
b3
b2
b1
The sub CPU writes the data to be written in the buffer memory in this register.
bit0
Reg.
b0
CPUBWDT
1-1-25. 1Ah
(1) SCTINF (sector information) register (read/write)
SCTINF (sector information) register
Adr.
bit7
bit6
bit5
bit4
bit3
1Ah (R/W)
SUBQ
FMSL
bit2
bit1
MODE2 FORM2
bit0
XFR
SCT
Reg.
SCTINF
While DECINT is active, the current sector information is written in this register. When making transfers to the
host automatically, be sure to set the information in this register each time DECINT is active. The value in this
register is written in the last address in the buffer memory area.
bit 7:
SUBQFMSL (subcode-Q format select)
High: When ENSBCBT is high and ALLSBC is low, the decoder does not write the subcode error
flag or 00h after subcode-Q in the buffer. When transferring the subcode error flag and 00h
after subcode-Q address data to the host, the sub CPU must write Data In the above
address before setting the SCTINF register.
Set this bit high only when ENSBCBT is high and ALLSBC is low is prohibited.
Low: When ENSBCBT is high and ALLSBC is low, the decoder writes the subcode error flag and
00h after subcode-Q in the buffer.
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