CXA3506R Datasheet, PDF (71/110 Pages) Sony Corporation – 3-channel 8-bit 120MSPS A/D Converter Amplifier PLL

CXA3506R
• EVEN/ODD function
When a toggle signal created by dividing the Vsync signal in half is input to the EVEN/ODD (Pin 108), the
ADC sampling clock is inverted every Vsync signal.
This function can be used to configure a single frame screen from two fields by AD converting an RGB
analog input signal that requires high speed and high resolution, such as a UXGA 60Hz (162MHz) or more
signal, at half the frequency of the original ADC sampling rate.
There are no particular control register settings when using the EVEN/ODD function. The sampling clock is
inverted based on the polarity of the signal input to the EVEN/ODD pin. Be sure to input signal to the
EVEN/ODD pin at TTL level.
EVEN/ODD pin
Operational mode
L
EVEN
H
ODD
Example of Using the EVEN/ODD Function
EVEN field
1
3
5
a
a
b
b
c
c
d
d
e
e
f
f
g
g
h
h
i
i
j
j
k
k
l
l
3
Analog input signal
1
5
ODD field
2
4
6
2
4
6
Hsync
Sampling CLK
Vsync
Toggle signal
(EVEN/ODD pin)
1
2
3
4
5
6
a
b
c
d
e
f
g
h
i
j
k
l
EVEN/ODD frame
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