CXA3506R Datasheet, PDF (47/110 Pages) Sony Corporation – 3-channel 8-bit 120MSPS A/D Converter Amplifier PLL

CXA3506R
PLL
• SYNC signal input
The SYNC (HSYNC) used by the PLL is input from the SYNC signal input pins. There are two sets of input
pins, SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112), which are switched by the control register.
SYNCIN1 input, SYNCIN2 input switching
Register: HSYNC1/2
SYNC signal input pin
0
SYNCIN1
1
SYNCIN2
SYNC signals within the range from 10kHz to 100kHz can be input. The input supports both positive and
negative polarity.
SYNC signal input polarity
Register: SYNC POL
SYNC signal input polarity
0
Negative
1
Positive
Set the register in accordance with the polarity of the externally input SYNC.
When SYNC is positive polarity, set SYNC POL to "1". (Clock is generated in sync with the rising edge of
SYNC.)
When SYNC is negative polarity, set SYNC POL to "0". (Clock is generated in sync with the falling edge of
SYNC.)
When there is no SYNC input, the VCO oscillates at random and a random pulse is output from the CLK output.
SYNC signal
LPF
PD
CP
VCO
A _DIV
1, 2, 4 ,8
B
Programmable
counter
Point A: VCO oscillation frequency
Point B: Clock frequency
• Phase detector (PD)
The phase detector compares the phase of the SYNC signal with that of the programmable counter output
signal. The phase comparison is performed at the edge, and a phase difference between the compared
signals is output as a pulse.
There is no hysteresis function for the input pins of the SYNC signal (SYNCIN1 and SYNCIN2) input to the
phase detector. If necessary external waveform shaping should be done as jitter results when a noisy signal
is input. Set the control register, PD POL, to "1" as for the input polarity of the phase detector.
• Hold function
The hold function holds the VCO input voltage and generates oscillation itself without performing phase
comparison. The VCO oscillation frequency is held during this period without performing phase comparison,
by inputting the HOLD signal from the HOLD (Pin 106).
HOLD signal polarity can be set by using the control register: HOLD POL.
Register: HOLD POL
HOLD signal input polarity
0
1
Held while HOLD signal is Low Held while HOLD signal is High
For details, see the hold timing diagram.
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