CXD2510Q Datasheet, PDF (5/48 Pages) Sony Corporation – CD Digital Signal Processor

CXD2510Q
Pin
No.
Symbol
I/O
Description
66 SQSO O 1, 0 Sub Q 80-bit and PCM peak and level data 16-bit output.
67 SQCK I
SQSO readout clock input.
68 MUTE I
High: mute; low: release
69 SENS — 1, Z, 0 SENS output to CPU.
70 XRST I
System reset. Reset when low.
71 DATA I
Serial data input from CPU.
72 XLAT I
Latch input from CPU. Serial data is latched at the falling edge.
73 VDD
Power supply (5V).
74 CLOK I
Serial data transfer clock input from CPU.
75 SEIN I
SENS input from SSP.
76 CNIN I
Track jump count signal input.
77 DATO O 1, 0 Serial data output to SSP.
78 XLTO O 1, 0 Serial data latch output to SSP. Latched at the falling edge.
79 CLKO O 1, 0 Serial data transfer clock output to SSP.
80 MIRR I
Mirror signal input.
Notes)
• The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement
output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
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