CXD1804AR Datasheet, PDF (45/103 Pages) Sony Corporation – CD-ROM Decoder

CXD1804AR
1-1-46. 48h, 49h
(1) BFFLRT-H, L (buffer full ratio-high, low) register (read/write)
BFFLRT-H, L (buffer full ratio-high, low) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
48h (R/W)
b10
b9
b8
BFFLRT-H
49h (R/W) b7
b6
b5
b4
b3
b2
b1
b0
BFFLRT-L
These registers indicate the buffer full ratio.
Note that bits 7 to 3 of BFFLRT-H should normally be set low.
1-1-47. 4Ah, 4Bh
(1) TIMER-H, L (timer-high, low) register (read/write)
TIMER-H, L (timer-high, low) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
4Ah (R/W) b15
b14
b13
b12
b11
b10
b9
b8
TIMER-H
4Bh (R/W) b7
b6
b5
b4
b3
b2
b1
b0
TIMER-L
These are the timer settings. The sub CPU should set these registers in the order of TIMER-H, L. After a value
is set in TIMER-L, a timer interrupt occurs when the time specified by (TIMER-H, L) ∗TIMRRSL passes.
1-1-48. 4Ch
(1) TMRRSL (timer resolution) register (read/write)
TMRRSL (timer resolution) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
4Ch (R/W) b7
b6
b5
b4
b3
b2
b1
b0
TMRRSL
This register determines the timer resolution. Assuming the XTL1 clock cycle to be Tw, the timer resolution is
TIMRRSL × 16 × Tw.
[Example] Setting a resolution of 100µs
(1) XTL1 = 40MHz (Tw = 25ns)
100 × 1000 / (16 × 25) = 250 (FAh)
Set FAh in this register. The resolution becomes 100µs.
(2) XTL1 = 33.8688 MHz (Tw = 29.5ns)
100 × 1000 / (16 × 29.5) = 211.68
Set D3 or D4h in this register. The resolution becomes 96.7µs or 100.2µs, respectively.
1-1-49. 4Eh, 4Fh
(1) STARTARA-H, L (start area-high, low) register (read)
STARTARA-H, L (start area-high, low) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
4Eh (R)
b8 STARTARA-H
4Fh (R)
b7
b6
b5
b4
b3
b2
b1
b0 STARTARA-L
These registers indicate the area from which transfer starts when executing stream processing.
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