CXD1804AR Datasheet, PDF (24/103 Pages) Sony Corporation – CD-ROM Decoder

CXD1804AR
bit 6:
bit 5:
bits 4, 3:
LCHLOW (Lch low)
High: When LRCK is low, determined to be the left channel data.
Low: When LRCK is high, determined to be the right channel data.
BCKRED (BLCK rising edge)
High: Data is strobed at the rising edge of BCLK.
Low: Data is strobed at the falling edge of BCLK.
BCKMD1, 0 (BCLK mode 1, 0)
These bits are set according to the number of clocks output for BCLK during 1/2 LCLK cycle by the
CD digital signal processing LSI (CD DSP).
BCKMD1
"L"
"L"
"H"
BCKMD0
"L"
"H"
"X"
16BCLKs/WCLK
24BCLKs/WCLK
32BCLKs/WCLK
bit 2:
bit 1:
bit 0
LSB1ST (LSB first)
High: Connected with the CD DSP which outputs data with LSB first.
Low: Connected with the CD DSP which outputs data with MSB first.
RESERVED
Normally set low.
Any change to the bits in this register must be made in the decoder disable status. (After the IC is
reset, the address is 28h.)
BFSHDFSL (buffering subheader flag select)
High: The Sub Headers written two times are compared and, if they do not match, the result
reports an error to bits 3 to 0 of BFHDRFLG.
Low: When the C2PO of the Sub Headers written two times are both high, that reports an error to
the bits 3 to 0 of BFHDRFLG.
1-1-4. 03h
(1) RAWMD (raw mode) register (read)
RAWMD (raw mode) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
03h (R)
RAWMD
The Header Mode byte for the sector being sent from the CD DSP while DECINT is active can be read from
this register.
(2) RFINTVL (refresh interval) register (write)
RFINTVL (refresh interval) register
Adr.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reg.
03h (W)
b7
b6
b5
b4
b3
b2
b1
b0
RFINTVL
This register determines the refresh interval. The refresh interval is RFINTVL × 4 × TW. Here, TW represents
the XTL1 clock frequency. Note that this IC performs RAS only refresh.
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