ICX085AK Datasheet, PDF (4/19 Pages) Sony Corporation – Diagonal 11mm (Type 2/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

ICX085AK
Bias Conditions
Item
Supply voltage
Substrate voltage adjustment range
Protective transistor bias
Symbol
VDD
VSUB
VL
Min.
14.55
5.5
Typ.
15.0
∗2
Max. Unit Remarks
15.45
V
12.5
V
∗1
DC Characteristics
Item
Symbol Min.
Typ.
Max. Unit Remarks
Supply current
IDD
6
8
mA
∗1 _{Indications of substrate voltage (VSUB) setting value}
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.
VSUB code – two characters indication
↑↑
Integer portion Decimal portion
Integer portion of code and optimal setting correspond to each other as follows.
Integer portion of code A C d E f G h J
Optimal setting
5 6 7 8 9 10 11 12
<Example> “G5”→ VSUB = 10.5V
∗2 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL}
power supply for the V driver should be used.
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH02
–0.05 0 0.05 V
2
VVH = VVH02
VVH1,VVH2,VVH3 –0.2 0 0.05 V
2
VVL1,VVL2,VVL3 –8.0 –7.5 –7.0 V
2
VVL = (VVL1 + VVL3)/2
Vφ1, Vφ2, Vφ3 6.8
Vertical transfer clock
voltage
| VVL1–VVL3 |
VVHH
7.5 8.05 V
0.1 V
0.5 V
2
2
2 High-level coupling
VVHL
0.5 V
2 High-level coupling
VVLH
0.5 V
2 Low-level coupling
VVLL
0.5 V
2 Low-level coupling
Horizontal transfer
VφH
clock voltage
VHL
4.75 5.0 5.25 V
3
–0.05 0 0.05 V
3
VφRG
4.5 5.0 5.5 V
4 Input through 0.01µF capacitance
Reset gate clock
voltage
VRGLH–VRGLL
0.8 V
VRGH
VDD
+0.4
VDD
+0.6
VDD
+0.8
V
4 Low-level coupling
4
Substrate clock voltage VφSUB
21.5 22.5 23.5 V
5
–4–