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ICX080AK Datasheet, PDF (3/19 Pages) Sony Corporation – Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras | |||
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ICX080AK
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
11.64 12.0 12.36 V
VL
â1
ÏSUB
â2
ÏRG
â2
â1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
â2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
6.0
Max. Unit Remarks
mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
11.64 12.0 12.36 V
VVH1, VVH2
â0.05 0 0.05 V
VVH3, VVH4
â0.2 0 0.05 V
VVL1, VVL2,
VVL3, VVL4
â6.85 â6.5 â6.15 V
VÏV
5.95 6.5 6.9 V
Vertical transfer clock
voltage
VVH3 â VVH
VVH4 â VVH
â0.25
â0.25
0.1 V
0.1 V
VVHH
0.5 V
VVHL
0.5 V
VVLH
0.5 V
VVLL
0.5 V
VÏH
Horizontal transfer
clock voltage
VHL
VCR
2.7 3.3 3.6 V
â0.05 0 0.05 V
0.5 1.65
V
Reset gate clock
voltage
VÏRG
2.7 3.3 3.6 V
VRGLH â VRGLL
0.4 V
VRGL â VRGLm
0.5 V
Substrate clock voltage VÏSUB
17.3 18.5 19.3 V
1
2
VVH = (VVH1 + VVH2)/2
2
2
VVL = (VVL3 + VVL4)/2
2
VÏV = VVHn â VVLn (n = 1 to 4)
2
2
2
High-level coupling
2
High-level coupling
2
Low-level coupling
2
Low-level coupling
3
3
3
Cross-point voltage
4
4
Low-level coupling
4
Low-level coupling
5
â3â
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