CXP88132 Datasheet, PDF (17/25 Pages) Sony Corporation – CMOS 8-bit Single Chip Microcomputer

CXP88132/88140
Fig. 3. Event count clock timing
TEX
EC0
EC1
EC2
0.8VDD
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol Pin
Condition
Min.
Max. Unit
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
floating delay time
CS0 ↓ → SO0
delay time
tDCSK SCK0
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
tDCSO SO0 _{Chip select transfer mode}
tsys + 200 ns
tsys + 200 ns
tsys + 200 ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0 _{Chip select transfer mode}
tsys + 200 ns
CS0
high level width
tWHCS CS0 _{Chip select transfer mode} tsys + 200
ns
SCK0
cycle time
Input mode
2tsys + 200
ns
tKCY SCK0
Output mode
16000/fc
ns
SCK0
high and low level widths
tKH
Input mode
tKL
SCK0
Output mode
tsys + 100
8000/fc – 50
ns
ns
SI0 input set-up time
(against SCK0 ↑)
SI0 input hold time
(against SCK0 ↑)
SCK0 ↓ → SO0 delay time
tSIK
SI0
SCK0 input mode
SCK0 output mode
tKSI
SI0
SCK0 input mode
SCK0 output mode
SCK0 input mode
tKSO _SO0
SCK0 output mode
100
ns
200
ns
tsys + 200
ns
100
ns
tsys + 200 ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 17 –