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CXP88132 Datasheet, PDF (16/25 Pages) Sony Corporation – CMOS 8-bit Single Chip Microcomputer
CXP88132/88140
∗1 RST pin is specified when evaluation mode is in use.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗3 When built-in pull-down resistor is selected with mask option.
∗4 When entire output pins are open.
∗5 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 0002FEH) to "00"
and operating in high speed mode (1/2 dividing clock).
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol Pin
Condition
Min. Typ. Max. Unit
System clock frequency
fC
System clock input pulse width
tXL,
tXH
System clock input rise and
tCR,
fall times
tCF
Event count clock input
tEH,
pulse width
tEL
Event count clock input
tER,
rise and fall times
tEF
System clock frequency
fC
XTAL
Fig. 1, Fig. 2
EXTAL
1
XTAL Fig. 1, Fig. 2
EXTAL External clock drive
28
XTAL Fig. 1, Fig. 2
EXTAL External clock drive
EC0, EC1,
EC2
Fig. 3
tsys + 200∗
EC0, EC1,
EC2
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applying condition)
32.768
16 MHz
ns
200 ns
ns
20 ms
kHz
Event count clock input
pulse width
tTL,
tTH
TEX
Fig. 3
10
µs
Event count clock input
rise and fall times
tTR,
tTF
TEX
Fig. 3
20 ms
∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
EXTAL
XTAL
VDD – 0.4V
0.4V
Fig. 2. Clock applying condition
Crystal oscillation
Ceramic oscillation
tXH
tCF
External clock
tXL
tCR
32kHz clock applying condition
Crystal oscillation
EXTAL XTAL
C1
C2
EXTAL XTAL
74HC04
TEX
C1
TX
C2
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