CXP84412 Datasheet, PDF (13/19 Pages) Sony Corporation – CMOS 8-bit Single Chip Microcomputer

CXP84412/84416
Fig. 3. Event count clock timing
TEX
EC
0.8VDD
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss reference)
Item
Symbol Pin
Condition
Min.
Max. Unit
CS0 ↓ → SCK0 (CS1 ↓ → SCK1) _tDCSK SCK0 Chip select transfer mode
delay time
(SCK1) (SCK0 (SCK1) = output mode)
1.5tsys + 200 ns
CS0 ↑ → SCK0 (CS1 ↑ → SCK1) _tDCSKF SCK0 Chip select transfer mode
float delay time
(SCK1) (SCK0 (SCK1) = output mode)
1.5tsys +200 ns
CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time
tDCSO
SO0
(SO1)
Chip select transfer mode
1.5tsys + 200 ns
CS0 ↑ → SO0 (CS1 ↑ → SO1)
float delay time
tDCSOF ^SO0 _{Chip select transfer mode}
(SO1)
1.5tsys + 200 ns
CS0 (CS1) High level width
tWHCS ^CS0
(CS1)
Chip select transfer mode
tsys + 200
ns
SCK0 (SCK1) cycle time
tKCY
SCK0 ^{Input mode}
(SCK1) _{Output mode}
2tsys + 200
ns
16000/fc
ns
SCK0 (SCK1)
High, Low level width
tKH
SCK0 ^{Input mode}
tKL
(SCK1) _{Output mode}
tsys + 100
ns
8000/fc – 50
ns
SI0 (SI1) input set-up time
(for SCK0 ↑ (SCK1 ↑) )
tSIK
SI0
(SI1)
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
100
200
ns
ns
SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )
tKSI
SI0
(SI1)
SCK0 (SCK1) input mode tsys + 200
SCK0 (SCK1) output mode 100
ns
ns
SCK0 ↓ → SO0 (SCK1 ↓ → SO1)
delay time
tKSO
SO0 ^{SCK0 (SCK1) input mode}
(SO1) _{SCK0 (SCK1) output mode}
tsys + 200 ^ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
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