CXA1690Q Datasheet, PDF (13/18 Pages) Sony Corporation – Head Amplifier for Digital CCD Cameras

CXA1690Q
CDS:
The CCD signal from the CCD image sensor enters PIN and DIN where it is correlated double sampled
(CDS: Correlated Double Sampling) by SH1, SH2 and SH3. The precharge level of the CCD output signal is
sampled-and-held and output by the SH2 output, and the signal level is sampled-and-held and output by the
SH3 output.
CDSCLP:
The CDSCLP stabilizes the DC level of the input signal, clamps (CLPDM) the input signal during the dummy
pixel interval for the purpose of eliminating the AGC input offset, and combines the DC level ([^∗1], [^∗2]) of
SH2 and SH3.
AGC:
The gain can be varied with the AGCMAX and AGCCONT voltage control (20/50) VCC to VCC. The maximum
gain can be varied from 19 to 43dB for AGCMAX, and from 7.9 to 43dB for AGCCONT.
LPF:
A primary low-pass filter has been installed for the purpose of eliminating unused bands and white noise and
improving S/N.
CAMSH:
The CAMSH is used for camera system signal processing. It is a sample-and-hold circuit which synchronizes
the data read-in timing for the external A/D. The slew rate of the input signal for the sample-and-hold circuit
can be controlled by adjusting the input current to the CSHI pin.
AGCCLP:
The basic black level is set ([^∗3]) by clamping it with the CLPOB clock during the OPB interval of the AGC
output waveform. The capacitance for AGCCLP is connected to the AGCCLP pin.
BLK:
The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not
fall below the basic black level and replacing the DC potential. ([^∗4])
The signal is blanked when PBLK is low.
C/VSW:
When the CAM/VIDEO and PB/REC pin voltages are set so that the camera signal processing system
operates, C/VSW leads the BLK output (camera signal) into the DRV. In addition, when these voltages are
set so that the video signal processing system operates, C/VSW leads the VISH output (video signal) into the
DRV.
CLPSW:
By selecting the CAM/VIDEO and PB/REC pin voltages, either [CAMCLP] is connected and lead into the
CLPDRV pin as the clamp for the output signal of the camera signal processing system, or [LOUTCLP] as
the clamp for the LIN mode output signal or [RFDC] as the DC shift for the PBREC mode output signal of the
video signal processing system.
DRV:
DRV drives the external A/D. RF mode or LIN mode signals for either the camera or video signals are input
to the DRV and output from DRVOUT by switching C/VSW.
CAMCLP:
The signal black level interval is clamped by the CLPDM clock to bring camera system signals within the
allowable input voltage range for the external A/D, and the signals are output to CLPOUT. ([^∗5])
In addition, the CAMCLP contains an OFFSET control pin which adjusts the CLP potential for the purpose of
compensating the clamp level difference generated by the DRV.
REFBOTTOM, REFTOP:
REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRB
and VRT, and supply 2V and 4V to the A/D.
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