CXD3027R Datasheet, PDF (121/191 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo + Shock-Proof Memory Controller + Digital High & Bass Boost

CXD3027R
§4-8. CD-DSP Block Playback Speed
In the CXD3027R, the following playback modes can be selected through different combinations of the XTAI,
XTSL pins, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division
commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.
Mode XTAI
XTSL
DSPB VCOSEL1^∗1 ASHS
Playback
speed
Error correction^∗2
1
768Fs
1
0
0/1
0
1×
C1: double; C2: quadruple
2
768Fs
1
1
0/1
0
2×
C1: double; C2: double
3
768Fs
0
0
1
1
2×
C1: double; C2: quadruple
4
768Fs
0
1
1
1
4×
C1: double; C2: double
5
384Fs
0
0
0/1
0
1×
C1: double; C2: quadruple
6
384Fs
0
1
0/1
0
2×
C1: double; C2: double
7
384Fs
1
1
0/1
0
1×
C1: double; C2: double
∗1 _{Actually, the optimal value should be used together with KSL3 and KSL2.}
∗2 _{When $8 command ERC4 = 1, C2 is quadruple correction even when DSPB = 1.}
The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for
details.
§4-9. Description of DAC Block and Shock-Proof Memory Controller Block Circuits
The CXD3027R inputs data from the CD-DSP block to the DAC block via the shock-proof memory controller
block.
The data from the shock-proof memory controller block is output externally as bass-boosted data via the DBB
circuit.
When not using the DAC block, the data from the shock-proof memory controller block can be output directly to
the outside of the LSI.
Also, when not using the shock-proof memory controller, the data can be input directly from the CD-DSP block
to the DAC block.
The DAC block output format supports 16, 18 or 20 bits.
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