EMC6D103_07 Datasheet, PDF (84/92 Pages) SMSC Corporation – Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

8.2.42
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
01=twice a second
1x=every 300msec
Bit[2] Snap to Zero (SZEN)
This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero.
0=Step Down the PWMx output to Off at the programmed Ramp Rate
1=Transition PWMx to Off immediately when the calculated duty cycle is 00h (default)
Bit[4:3] Guard time (Mode 2 only)
00=63 clocks (90kHz clocks ~ 700usec)
01=32 clocks (90kHz clocks ~ 356usec) (default)
10=16 clocks (90kHz clocks ~ 178usec)
11=8 clocks (90kHz clocks ~ 89usec)
Bit[5] Opportunistic Mode Enable
0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0]
in this register)
1=Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid
tachometer reading can be made without stretching the PWM output signal. If a valid reading is
detected prior to the Update cycle, then the Update counter is reset.
Bit[7:6] Reserved
Register 97h: SMSC Test Register
Register Read
Address /Write
97h
R/W
Table 8.63 Register 97h: SMSC Test Register
Register Name
SMSC Test Register
Bit 7
(MSb)
TST7
Bit 6
TST6
Bit 5
TST5
Bit 4
TST4
Bit 3
TST3
Bit 2
TST2
Bit 1
TST1
Bit 0
(LSb)
TST0
Default
Value
5Ah
8.2.43
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This is an SMSC Test Register. Writing to this register may cause unwanted results.
Register 98h:SMSC Test Register
Register Read
Address /Write
98h
R/W
Table 8.64 Register 98h:SMSC Test Register
Register Name
SMSC Test Register
Bit 7
(MSb)
TST7
Bit 6
TST6
Bit 5
TST5
Bit 4 Bit 3
TST4 TST3
Bit 2
TST2
Bit 1
Bit 0 Default
(LSb) Value
TST1 TST0 F1h
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This is an SMSC Test Register. Writing to this register may cause unwanted results.
Revision 0.3 (03-01-07)
84
DATASHEET
SMSC EMC6D103