EMC6D103_07 Datasheet, PDF (71/92 Pages) SMSC Corporation – Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
Ramp Rate Control
The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time.
This period of time is programmable via the Ramp Rate Control bits. For a detailed description of the
Ramp Rate Control bits see Table 8.33. For a description of the Ramp Rate Control logic see Ramp
Rate Control Logic on page 38.
Note:
„ RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
„ RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
„ RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
„ RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
Table 8.33 PWM Ramp Rate Control
RRX-[2:0]
000
001
010
011
100
101
110
111
PWM RAMP TIME
(SEC)
(TIME FROM 33%
DUTY CYCLE TO
100% DUTY CYCLE)
35
17.6
11.8
7.0
4.4
3.0
1.6
0.8
PWM RAMP TIME
(SEC)
(TIME FROM 0%
DUTY CYCLE TO
100% DUTY CYCLE)
52.53
26.52
17.595
10.455
6.63
4.59
2.55
1.275
TIME PER PWM STEP
(PWM STEP SIZE =
1/255)
PWM
RAMP RATE
(HZ)
206 msec
4.85
104 msec
9.62
69 msec
14.49
41 msec
24.39
26 msec
38.46
18 msec
55.56
10 msec
100
5 msec
200
8.2.19 Registers 64-66h: Minimum PWM Duty Cycle
Register
Address
64h
65h
66h
Read/
Write
R/W
R/W
R/W
Table 8.34 Registers 64-66h: Minimum PWM Duty Cycle
Register Name
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
Bit 7
(MSb)
7
7
7
Bit 6
6
6
6
Bit 5
5
5
5
Bit 4 Bit 3 Bit 2
4
3
2
4
3
2
4
3
2
Bit 1
1
1
1
Bit 0
(LSb)
0
0
0
Default
Value
80h
80h
80h
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
These registers specify the minimum duty cycle that the PWM will output when the measured
temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode.
SMSC EMC6D103
71
DATASHEET
Revision 0.3 (03-01-07)