37M602 Datasheet, PDF (77/182 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT

Table 35 - Register Summary for an Individual UART Channel
REGISTER
REGISTER
ADDRESS*
REGISTER NAME
SYMBOL
BIT 0
BIT 1
ADDR = 0
DLAB = 0
Receive Buffer Register (Read Only)
RBR
Data Bit 0 Data Bit 1
(Note 1)
ADDR = 0
DLAB = 0
Transmitter Holding Register (Write
Only)
THR Data Bit 0 Data Bit 1
ADDR = 1
DLAB = 0
Interrupt Enable Register
IER Enable
Enable
Received Transmitter
Data
Holding
Available Register
Interrupt Empty
(ERDAI)
Interrupt
(ETHREI)
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
"0" if
Interrupt ID
Interrupt Bit
Pending
ADDR = 2
FIFO Control Register (Write Only)
FCR
FIFO
(Note 7) Enable
RCVR FIFO
Reset
ADDR = 3
Line Control Register
LCR
Word
Length
Select Bit 0
(WLS0)
Word
Length
Select Bit 1
(WLS1)
ADDR = 4
MODEM Control Register
MCR
Data
Terminal
Ready
(DTR)
Request to
Send (RTS)
ADDR = 5
Line Status Register
LSR Data Ready Overrun
(DR)
Error (OE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear Delta Data
to Send
Set Ready
(DCTS)
(DDSR)
ADDR = 7
ADDR = 0
DLAB = 1
Scratch Register (Note 4)
Divisor Latch (LS)
SCR
DDL
Bit 0
Bit 0
Bit 1
Bit 1
ADDR = 1
Divisor Latch (MS)
DLM Bit 8
Bit 9
DLAB = 1
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift
register is empty.
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