LPC47B27X Datasheet, PDF (64/196 Pages) SMSC Corporation – 100 PIN ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT
FIFOs are still fully capable of holding characters.
DESIRED
BAUD RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
Table 30 - Baud Rates
DIVISOR USED TO
PERCENT ERROR DIFFERENCE
GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL¹
2304
0.001
1536
-
1047
-
857
0.004
768
-
384
-
192
-
96
-
64
-
58
0.005
48
-
32
-
24
-
16
-
12
-
6
-
3
0.030
2
0.16
1
0.16
32770
0.16
32769
0.16
Note¹: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note ²: The High Speed bit is located in the Device Configuration Space.
HIGH
SPEED BIT²
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Table 31 - Reset Function
REGISTER/SIGNAL
RESET CONTROL
Interrupt Enable Register
RESET
Interrupt Identification Reg. RESET
FIFO Control
RESET
Line Control Reg.
RESET
MODEM Control Reg.
RESET
Line Status Reg.
RESET
MODEM Status Reg.
RESET
TXD1
RESET
TXD2
RESET
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
RESET STATE
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
See Note 1
See IR Transmit Pins on page 69
Low
Low
Low
High
High
High
High
All Bits Low
All Bits Low
SMSC LPC47B27x
- 64 -
DATASHEET
Rev. 08-10-04