LPC47B27X Datasheet, PDF (136/196 Pages) SMSC Corporation – 100 PIN ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

NAME
SMI_EN2
Default = 0x00
on VTR POR
SMI_EN3
Default = 0x00
on VTR POR
SMI_EN4
Default = 0x00
on VTR POR
SMI_EN5
Default = 0x00
on VTR POR
N/A
SMSC LPC47B27x
REG OFFSET
(hex)
17
(R/W)
18
(R/W)
19
(R/W)
1A
(R/W)
1B
(R)
DESCRIPTION
SMI Enable Register 2
This register is used to enable the different interrupt sources
onto the group nSMI output, and the group nSMI output onto
the nIO_SMI GPI/O pin, the serial IRQ stream or into the
PME Logic.
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_P12
Bit[5] EN_SMI_PME (Enable group SMI into PME logic)
Bit[6] EN_SMI_S (Enable group SMI onto serial IRQ)
Bit[7] EN_SMI (Enable group SMI onto nIO_SMI pin)
SMI Enable Register 3
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] Reserved
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP60
SMI Enable Register 4
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP42
Bit[6] GP43
Bit[7] GP61
SMI Enable Register 5
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP54
Bit[1] GP55
Bit[2] GP56
Bit[3] GP57
Bit[4] Reserved
Bit[5] Reserved
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
Reserved – reads return 0
- 136 -
DATASHEET
Rev. 08-10-04