FDC37B72X_07 Datasheet, PDF (63/238 Pages) SMSC Corporation – 128 Pin Enhanced Super I/O Controller with ACPI Support

Sense Interrupt Status command is issued after
the Seek command to terminate it and to provide
verification of the head position (PCN). The H bit
(Head Address) in ST0 will always return to a "0".
When exiting POWERDOWN mode, the FDC
clears the PCN value and the status information to
zero. Prior to issuing the POWERDOWN
command, it is highly recommended that the user
service all pending interrupts through the Sense
Interrupt Status command.
Sense Interrupt Status
An interrupt signal on FINT pin is generated by the
FDC for one of the following reasons:
1. Upon entering the Result Phase of:
a. Read Data command
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Track command
g. Write Deleted Data command
h. Verify command
2. End of Seek, Relative Seek, or Recalibrate
command
3. FDC requires a data transfer during the
execution phase in the non-DMA mode
The Sense Interrupt Status command resets the
interrupt signal and, via the IC code and SE bit of
Status Register 0, identifies the cause of the
interrupt.
INTERRUPT IDENTIFICATION
SE IC
INTERRUPT DUE TO
0
11 Polling
1
00 Normal termination of Seek
or Recalibrate command
Abnormal termination of
1
01 Seek or Recalibrate
command
The Seek, Relative Seek, and Recalibrate
commands have no result phase. The Sense
Interrupt Status command must be issued
immediately after these commands to terminate
them and to provide verification of the head
position (PCN). The H (Head Address) bit in ST0
will always return a "0". If a Sense Interrupt Status
is not issued, the drive will continue to be BUSY
and may affect the operation of the next
command.
Sense Drive Status
Sense Drive Status obtains drive status
information. It has not execution phase and goes
directly to the result phase from the command
phase. Status Register 3 contains the drive status
information.
Specify
The Specify command sets the initial values for
each of the three internal times. The HUT (Head
Unload Time) defines the time from the end of the
execution phase of one of the read/write
commands to the head unload state. The SRT
(Step Rate Time) defines the time interval between
adjacent step pulses. Note that the spacing
between the first and second step pulses may be
shorter than the remaining step pulses. The HLT
(Head Load Time) defines the time between when
the Head Load signal goes high and the read/write
operation starts. The values change with the data
rate speed selection and are documented in Table
29. The values are the same for MFM and FM.
TABLE 30 - DRIVE CONTROL DELAYS (MS)
63