LAN9215I_07 Datasheet, PDF (59/138 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
3.13.2 RX Packet Format
The RX status words can be read from the RX status FIFO port, while the RX data packets can be
read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can
read them as shown in Figure 3.18. It is assumed that the host has previously read the associated
status word from the RX status FIFO, to ascertain the data size and any error conditions.
Host Read
Order
1st
2nd
Last
31
0
Optional offset DWORD0
.
.
Optional offset DWORDn
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
Optional Pad DWORD0
.
.
Optional Pad DWORDn
3.13.3
Figure 3.18 RX Packet Format
Note 3.16 The LAN9215i host bus interface supports 16-bit bus transfers; internally, all data paths
are 32-bits wide. Figure 3.18 describes the host read ordering for pairs of atomic 16-bit
transactions.
RX Status Format
BITS
31
30
29:16
15
14
13
DESCRIPTION
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
SMSC LAN9215i
59
DATASHEET
Revision 1.93 (12-12-07)