LPC47M172 Datasheet, PDF (56/227 Pages) SMSC Corporation – ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SYMBOL
N
NCN
ND
OW
PCN
POLL
PRETRK
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
WGATE
NAME
DESCRIPTION
Sector Size Code
This specifies the number of bytes in a sector. If this parameter is
"00", then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the "N'th" power) times 128. All values up
to "07" hex are allowable. "07"h would equal a sector size of 16k.
It is the user's responsibility to not select combinations that are not
possible with the drive.
N
SECTOR SIZE
00
128 Bytes
01
256 Bytes
02
512 Bytes
03
1024 Bytes
…
…
07
16K Bytes
New Cylinder The desired cylinder number.
Number
Non-DMA Mode Write ‘0’. This part does not support non-DMA mode.
Flag
Overwrite
The bits D0-D3 of the Perpendicular Mode Command can only be
modified if OW is set to 1. OW id defined in the Lock command.
Present Cylinder The current position of the head at the completion of Sense
Number
Interrupt Status command.
Polling Disable When set, the internal polling routine is disabled. When clear,
polling is enabled.
Precompensation Programmable from track 00 to FFH.
Start Track
Number
Sector Address
The sector number to be read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be
read or written.
Relative Cylinder Relative cylinder offset from present cylinder as used by the
Number
Relative Seek command.
Number of The number of sectors per track to be initialized by the Format
Sectors Per Track command. The number of sectors per track to be verified during a
Verify command when EC is set.
Skip Flag
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If
Read Deleted is executed, only sectors with a deleted address
mark will be accessed. When set to “0”, the sector is read or
written the same as the read and write commands.
Step Rate Interval The time interval between step pulses issued by the FDC.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at
the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Status 0
Status 1
Status 2
Registers within the FDC which store status information after a
command has been executed. This status information is available
to the host during the result phase after command execution.
Status 3
Write Gate
Alters timing of WE to allow for pre-erase loads in perpendicular
drives.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 56
DATASHEET
SMSC LPC47M172