LPC47M172 Datasheet, PDF (152/227 Pages) SMSC Corporation – ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0
NAME
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
PME_STS3
Default = 0x00
on VTR POR
PME_STS2
Default = 0x00
on VTR POR
REG OFFSET
(Type)
0x00
(R/W)
0x01 – 0x03
(R)
0x04
(R/W)
0x05 – 0x07
(R)
0x08
(R/W)
0x09
(R/W)
DESCRIPTION
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M172 would normally assert the
nIO_PME signal, independent of the state of the
PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M172 to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Bits[7:0] Reserved – reads return 0
Bit[0] PME_En
= 0 nIO_PME signal assertion is disabled (default)
= 1 Enables LPC47M172 to assert nIO_PME signal
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
Bits[7:0] Reserved – reads return 0
PME Wake Status Register 3
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP23
Bits[7:4] Reserved
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
PME Wake Status Register 2
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 152
DATASHEET
SMSC LPC47M172