COM20020D Datasheet, PDF (56/72 Pages) SMSC Corporation – ULANC Revision D Universal Local Area Network Controller with 2K x 8 On-Board RAM

A0-A2
nCS
nRD
nWR
D0-D7
VALID
t1
t2
t3
Note 3
t10
t6
t5
t8
VALID DATA
t4
t9
Note 2
t7
CASE 1: RBUSTMG bit = 0
Parameter
t1 Address Setup to nRD Active
t2 ^{Address Hold from nRD Inactive}
t3 nCS Setup to nRD Active
t4 nCS Hold from nRD Inactive
t5 ^{Cycle Time (nRD Low to Next Time Low)}
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 nRD Low Width
t9 nRD High Width
t10 nWR to nRD Low
min
15
10
5**
0
4TARB*
0
60
20
20
max units
nS
nS
nS
nS
nS
40** ^nS
20
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** ^{nCS may become active after control becomes active, but the access time (t6)}
will now be 45nS measured from the leading edge of nCS.
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
**Note 2:
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
FIGURE 15A - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ
CYCLE
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