COM20020D Datasheet, PDF (13/72 Pages) SMSC Corporation – ULANC Revision D Universal Local Area Network Controller with 2K x 8 On-Board RAM

SYSTEM DESCRIPTION
MICROCONTROLLER INTERFACE
The top halves of Figures 2 and 3 illustrate typical
COM20020D interfaces to the microcontrollers.
The interfaces consist of a 8-bit data bus, an
address bus and a control bus. In order to support
a wide range of microcontrollers without requiring
glue logic and without increasing the number of
pins, the COM20020D automatically detects and
adapts to the type of microcontroller being used.
Upon hardware reset, the COM20020D first
determines whether the read and write control
signals are separate READ and WRITE signals
(like the 80XX) or DIRECTION and DATA
STROBE (like the 68XX). To determine the type of
control signals, the device requires the software to
execute at least one write access to external
memory before attempting to access the
COM20020D. The device defaults to 80XX-like
signals. Once the type of control signals are
determined, the COM20020D remains in this
interface mode until the next hardware reset
occurs. The second determination the
COM20020D makes is whether the bus is
multiplexed or non-multiplexed. To determine the
type of bus, the device requires the software to
write to an odd memory location followed by a
read from an odd location before attempting to
access the COM20020D. The signal on the A0 pin
during the odd location access tells the
COM20020D the type of bus. Since multiplexed
operation requires A0 to be active low, activity on
the A0 line tells the COM20020D that the bus is
non-multiplexed. The device defaults to
multiplexed operation. Both determinations may
be made simultaneously by performing a WRITE
followed by a READ operation to an odd location
within the COM20020D Address space 20020D
registers. Once the type of bus is determined, the
COM20020D remains in this interface mode until
hardware reset occurs.
Whenever nCS and nRD are activated, the preset
determinations are assumed as final and will not
be changed until hardware reset. Refer to
Description of Pin Functions section for details on
the related signals. All accesses to the internal
RAM and the internal registers are controlled by
the COM20020D. The internal RAM is accessed
via a pointer-based scheme (refer to the
Sequential Access Memory section), and the
internal registers are accessed via direct
addressing. Many peripherals are not fast enough
to take advantage of high-speed microcontrollers.
Since microcontrollers do not typically have
READY inputs, standard peripherals cannot
extend cycles to extend the access time. The
access time of the COM20020D, on the other
hand, is so fast that it does not need to limit the
speed of the microcontroller. The COM20020D is
designed to be flexible so that it is independent of
the microcontroller speed.
The COM20020D provides for no wait state
arbitration via direct addressing to its internal
registers and a pointer based addressing scheme
to access its internal RAM. The pointer may be
used in auto-increment mode for typical
sequential buffer emptying or loading, or it can be
taken out of auto-increment mode to perform
random accesses to the RAM. The data within
the RAM is accessed through the data register.
Data being read is prefetched from memory and
placed into the data register for the microcontroller
to read. It is important to notice that only by
writing a new address pointer (writing to an
address pointer low), one obtains the contents of
COM20020D internal RAM. Performing only read
from the Data Register does not load new data
from the internal RAM. During a write operation,
the data is stored in the data register and then
written into memory. Whenever the pointer is
loaded for reads with a new value, data is
immediately prefetched to prepare for the first
read operation.
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