COM20019I Datasheet, PDF (53/65 Pages) SMSC Corporation – Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM

Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
A0-A2
nCS
nRD
nWR
D0-D7
VALID
t1
t2
t3
Note 3
t10
t6
t5
t8
VALID DATA
t4
t9
Note 2
t7
CASE 2: RBUSTMG bit = 1
Parameter
t1 Address Setup to nRD Active
t2 ^{Address Hold from nRD Inactive}
t3 nCS Setup to nRD Active
t4 ^{nCS Hold from nRD Inactive}
t5 ^{Cycle Time (nRD Low to Next Time Low)}
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 nRD Low Width
t9 nRD High Width
t10 nWR to nRD Low
min
max
-5
0
-5
0
4TARB*+30
60**
0
20
100
30
20
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
** t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.
Note 1: The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 2: _{Read cycle for Address Pointer Low/High Registers occurring after a read from}
Note 3:
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
SMSC COM20019I
Page 53
DATASHEET
Rev. 04-15-05