USB3300_07 Datasheet, PDF (40/55 Pages) SMSC Corporation – Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
Table 6.8 DP/DM termination vs. Signaling Mode (continued)
REGISTER SETTINGS
RESISTOR SETTINGS
SIGNALING MODE
Peripheral LS Resume
Peripheral Test J/Test K
OTG device, Peripheral Chirp
OTG device, Peripheral HS
OTG device, Peripheral FS
OTG device, Peripheral HS/FS Suspend
OTG device, Peripheral HS/FS Resume
OTG device, Peripheral Test J/Test K
10b 1b 10b 0b 0b 0b 1b 0b 0b 0b
00b 0b 10b 0b 0b 0b 0b 0b 0b 1b
00b 1b 10b 0b 1b 1b 0b 0b 1b 0b
00b 0b 00b 0b 1b 0b 0b 0b 1b 1b
01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
01b 1b 10b 0b 1b 1b 0b 0b 1b 0b
00b 0b 10b 0b 1b 0b 0b 0b 1b 1b
6.2.3
Note: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and
the biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance, external
reference resistor connected from RBIAS to ground.
6.3
Crystal Oscillator and PLL
The USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.
The USB3300 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.1. If a clock
oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a
external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an
external clock the user needs to take care to ensure the external clock source is clean enough to not
corrupt the high speed eye performance.
Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz
clock. The USB3300 is guaranteed to start the clock within the time specified in Table 5.2, "Electrical
Characteristics: CLKOUT Start-Up". The USB3300 does not support using an external 60MHz clock
input.
For Host Applications the USB3300 implements the ULPI AutoResume bit in the Interface Control
register. The default AutoResume state is 0 and this bit should be enabled for Host applications. For
more details please see sections 7.1.77 and 7.9 of the USB specification.
Revision 1.08 (11-07-07)
40
DATASHEET
SMSC USB3300