LPC47M192 Datasheet, PDF (22/228 Pages) SMSC Corporation – LPC SUPER I/O WITH HARDWARE MONITORING BLOCK

5 BLOCK DIAGRAM
CLK32
CLOCKI
SER_IRQ
PCI_CLK
LAD[3:0]
LFrame
LDRQ
PCI_RESET
LPCPD
IO_PME*
IO_SMI*
GP1[0:7]*
GP2[0:2,4:7]*
GP3[0:7]*, GP4[0:3]*
GP5[0:7]*, GP6[0:1]*
SDA
SCL
VID0
VID1
VID2
VID3
12V_IN/VID4
+5V_IN
+3.3V_IN
+2.5V_IN
+1.8V_IN
+1.5V_IN
Vccp_IN
HVCC
HVSS
A0/RESET#/THERM#/
XNOR_OUT
CLOCK
GEN
SERIAL
IRQ
LPC
Bus Interface
2nd Infrared Port
Game Port
Fan Control
Internal Bus
(Data, Address, and Control lines)
Power Mgmt
General
Purpose
I/O
SMBus
Hardware
Monitoring
LPC47M192
(128 QFP)
WDATA
WCLOCK
SMC PROPRIETARY
82077 COMPATIBLE
VERTICAL
FLOPPYDISK
CONTROLLER CORE
DIGITAL DATA
SEPARATOR
WITH WRITE
PRECOM-
PENSATION
RCLOCK
RDATA
LEDs
Multi-Mode
Parallel Port
with
ChiProtect^TM/
FDC MUX
(see LPC47B27x)
PD[7,0]
Busy, Slct, PE,
ERROR, ACK
STROBE, INIT, SLCTIN,
ALF
High-Speed
16550A
UART
PORT 1
High-Speed
16550A
UART
PORT 2
MPU-401
Serial Port
Keyboard/Mouse
8042
controller
TXD1, RXD1
CTS1, RTS1
DSR1, DTR1
DCD1, RI1
TXD2 (IRTX)*,
RXD2 (IRRX)*
CTS2*, RTS2 *
DSR2*, DTR2*
DCD2*, RI2*
MIDI_IN*
MIDI_OUT*
KCLK, MCLK
KDATA, MDATA
GateA20*
KRESET*
P12*, P16*, P17*
Note 1: This diagram does not show power and ground
connections.
Note 2: Functions with "*" are located on multifunctional pins.
This diagram is designed to show the various functions
available on the chip (not pin layout).
FIGURE 1 – LPC47M192 BLOCK DIAGRAM
SMSC DS – LPC47M192
Page 22
DATASHEET
Rev. 03/30/05