LPC47M192 Datasheet, PDF (148/228 Pages) SMSC Corporation – LPC SUPER I/O WITH HARDWARE MONITORING BLOCK

NAME
SMI_STS3
Default = 0x00
on VTR POR
SMI_STS4
Default = 0x00
on VTR POR
(Note 6)
SMI_STS5
Default = 0x00
on VTR POR
N/A
SMI_EN1
Default = 0x00
on VTR POR
SMSC DS – LPC47M192
REG OFFSET
(hex)
12
(R/W)
DESCRIPTION
SMI Status Register 3
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] Reserved
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP60
13
(R/W)
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP42
Bit[6] GP43
Bit[7] GP61
14
(R/W)
SMI Status Register 5
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP54
Bit[1] GP55
Bit[2] GP56
Bit[3] GP57
Bit[4] Reserved
Bit[5] Reserved
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
15
(R)
16
(R/W)
Bits[7:0] Reserved – reads return 0
SMI Enable Register 1
This register is used to enable the different interrupt
sources onto the group nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] EN_MPU-401 INT
Bit[6] Reserved
Bit[7] Reserved (Note 7)
Page 148
DATASHEET
Rev. 03/30/05