LPC47S45X_07 Datasheet, PDF (206/259 Pages) SMSC Corporation – Advanced I/O with X-Bus Interface

NAME
Primary Interrupt
Select
Default=0x00 or 0x06
(Note 1)
on VCC POR, VTR
POR,
PCI RESET
and
SOFT RESET
Table 85 − Interrupt Select Configuration Register Description
REG INDEX
0x70
(R/W)
DEFINITION
Bits[3:0] selects which interrupt level is used for the primary
Interrupt.
0x00= no interrupt selected
0x01= IRQ1
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Note: All interrupts are edge high (except ECP/EPP)
Note: nSMI is active low
Note: The polarity of IRQ8 is programmable via bit 0 of register
0xF1 in Logical Device A.
STATE
C
Bits[7:4] Reserved
Note: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND:
ƒ For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
ƒ For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
ƒ For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
ƒ For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
ƒ and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
ƒ For the KYBD logical device (refer to the KYBD controller section of this spec).
ƒ For the SMBus logical device by setting ENI, bit D3 of the Control Register.
Note: IRQs are disabled if not used/selected by any Logical Device. Refer to Note A.
Note: nSMI must be disabled to use IRQ2.
Note: All IRQ’s are available in Serial IRQ mode.
Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Table 86 − DMA Channel Select Configuration Register Description
NAME
DMA Channel Select
Default=0x02 or 0x04
(Note 1)
on VCC POR, VTR
POR, PCI RESET and
SOFT RESET
REG INDEX
0x74 (R/W)
DEFINITION
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
Note:
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
SMSC LPC47S45x
Page 206 of 259
DATASHEET
STATE
C
Rev. 04-30-07