LPC47B272 Datasheet, PDF (176/195 Pages) SMSC Corporation – 100 Pin Enhanced Super I/O Controller with LPC Interface

t1
t2
nWRITE
PD<7:0>
nDATASTB
nADDRSTB
t4
t5
t6
t3
t7
t8
t9
nWAIT
FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
DESCRIPTION
nWAIT Asserted to nWRITE Asserted (Note 1)
nWAIT Asserted to nWRITE Change (Note 1)
nWAIT Asserted to PDATA Invalid (Note 1)
PDATA Valid to Command Asserted
nWRITE to Command Asserted
nWAIT Asserted to Command Asserted (Note 1)
nWAIT Deasserted to Command Deasserted
(Note 1)
Command Asserted to nWAIT Deasserted
Command Deasserted to nWAIT Asserted
MIN TYP MAX UNITS
60
185
ns
60
185
ns
0
ns
10
ns
5
35
ns
60
210
ns
60
190
ns
0
10
µs
0
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is
considered to have settled after it does not transition for a minimum of 50 nsec.
SMSC LPC47B27x
- 176 -
DATASHEET
Rev. 04-17-07